When a plurality of semiconductor devices are formed in a substrate of single crystalline silicon, the active regions which contain these devices need to be electrically isolated from each other. One approach for effecting this isolation involves the selective removal of portions of the substrate, in order to define a trench or recess where an isolation region is needed. Then, a dielectric layer is introduced into the trench or recess to create the isolation region. In the case of a bulk silicon substrate, such a technique is commonly referred to as shallow trench isolation (STI). In the context of a semiconductor on insulator (SOI) substrate, such a technique is often referred to as mesa isolation.
On a more specific level, this known technique involves applying a blocking layer over the silicon substrate, selectively removing portions of the blocking layer and the substrate where an isolation region is needed, oxidizing, and then depositing the dielectric layer over the blocking layer and in the trench or recess. Then, a chemical-mechanical polishing step is carried out on the dielectric layer in order to remove portions of the dielectric layer disposed above the blocking layer, while leaving a planarized portion of the dielectric layer in the trench or recess. A small portion of the blocking layer may be incidentally removed with the upper portion of the dielectric layer. Although this known technique has been generally adequate for its intended purpose, it has not been satisfactory in all respects.
More specifically, it has been difficult with the chemical-mechanical polishing step to uniformly remove the dielectric material from the blocking layer across an entire wafer. There may be variations across the overall wafer, for example due to factors such as deformation of the polishing pad. There may also be variations on a smaller scale, for example in dependence on the size of respective active regions which are near each other, because the chemical-mechanical polishing process tends to remove material more rapidly over smaller active regions than over larger active regions.
One technique developed to reduce the effects of these problems is to carry out a reverse pattern etch prior to the chemical-mechanical polishing step. The reverse pattern etch selectively removes some of the dielectric material from the larger active regions so that, during the subsequent chemical-mechanical polishing, the removal of dielectric material from the larger active regions is completed at about the same time as the removal of dielectric material from the smaller active regions. However, this has not been entirely effective in eliminating problems, and involves significant added cost, because several additional steps are needed to carry out an etch process which is patterned.
Another known technique is to provide dummy moat or active regions, which are similar to true active regions except that no components are ultimately fabricated in these dummy regions. The purpose of these dummy active regions is to increase the cumulative area of active regions present in certain portions of the wafer, but this approach has also not satisfactorily eliminated the problems in question.